The present invention relates to a filter circuit for selecting packets from among a plurality of packets of a time division multiplexed data stream. More particularly this invention relates to a filter circuit for selecting packets based on the PID (packet identifier) incorporated in the packet, and to a FIFO (first-in first-out) memory used in the filter circuit.
A plurality of types of data may be transmitted in a single data stream as individual time division multiplexed packets. Each packet includes a packet identifier (PID) that denotes the type of data that the packet contains. When the packet is received, the PID may be used to determine whether the packet contains a desired type of data.
The well-known MPEG 2 (Moving Picture Experts Group 2) audio/video/data compression standard uses time division multiplexed data packets. Each TS (Transport Stream) packet has a fixed length of 188 bytes as shown in FIG. 1. The PID is thirteen bits long and is located twelve bits from the beginning of the packet.
In some cases, the position of the PID within a packet is not fixed. In the packet shown in FIG. 2, the position of the PID is not fixed within the packet. In such instances, the packet includes a pointer that indicates the location of the PID. In the example shown in FIG. 2, the pointer is located at the beginning of the packet.
In a system using time division multiplexed packets, the receiving side determines whether a received packet contains a desired type of data based on the packet ID. This process is implemented by a filter circuit that samples packets having predetermined PIDs from the packet stream.
FIG. 3 is a block diagram showing one example of a configuration of a conventional PID filter circuit. In the example of FIG. 3, the PID has a length of three words.
The filter circuit includes flip-flops (FF) 61 to 63 that delay the input packet data by a length of three words. An output of the flip-flop 63 of the last stage is provided to a FIFO (First-in First-out) memory 60 for implementing first-in first-out storage of the received packet data. Further, the outputs of the flip-flops 61 to 63 are provided to respective comparators 64 to 66 that compare the inputs from the flip-flops with predetermined data. The outputs of the respective comparators 64 to 66 are inputted to a three input AND gate 67, and the output of the AND gate controls the writing of data in the FIFO.
The PID filter circuit of FIG. 3 operates as follows. The respective flip-flops 61 to 63 delay the input data by one word. The comparator 64, the comparator 65 and the comparator 66 perform a comparison on respective sequential words of the received data. Therefore three continuous words are simultaneously delayed by the flip-flops 61 to 63 and three continuous words are compared by the comparators 64 to 66 at the same time. When the three words that constitute the PID of the received data are received by the comparators and are found to be the same as the predetermined PID words, the comparator provides an appropriate signal to the AND gate 67 and the output of the AND gate 67 is used as a control signal to enable writing of the input packet into the FIFO memory 60.
However, the conventional circuit of FIG. 1 suffers from the problems described below.
Figure First, the example of FIG. 3 is designed to operate only on a PID having a fixed length of three words. To operate on data having PIDs that are five words in length, five flip-flops and five comparators would be required. Furthermore, the circuit cannot use a simple two input AND gate since the number of inputs to the AND gate depends on the number of words in the PID. Therefore a complicated circuit is required.
Second, the example of FIG. 3 requires that the position of the PID within the packet data is fixed. In the example shown in FIG. 3, it is necessary for the PID to be located at the beginning of the packet data, in order to provide the correct data to the comparators and hence to store desired packets in the FIFO memory 60. For instance, if the PID begins at the third word of the packet, it is necessary to provide two additional flip-flops in between the flip-flop 63 and the FIFO memory 60. Furthermore, the PID must be provided at the same position in each packet, and therefore the circuit of FIG. 3 cannot be used where the position of the PID is variable.
Thus the operation of the conventional circuit depends upon the PID having a fixed length and a fixed position within the packet.
In view of the foregoing, it is an object of the present invention to provide a PID filter circuit which may be configured to operate on PIDs having varying lengths and having varying positions within the packet data, and which includes a FIFO memory.
According to a first aspect of the present invention, in order to achieve the above-mentioned object, there is provided a PID filter circuit for implementing a filtering of packet data on the basis of PIDs (Packet Identifiers). The PID filter circuit includes a comparison value table for storing therein a comparison value that is used to identify PIDs, and a comparator for determining the stored position of a PID within an input packet, for reading words of a comparison value successively from the comparison value table, and for comparing the words of the PID of the input packet with words of the comparison value taken from the comparison value table on a word by word basis.
According to a second aspect of the present invention, a PID filter circuit includes a FIFO (First-in, First-out) memory for storing input packet data. The FIFO memory does not execute a read operation for an input packet until the input packet is determined to be desired data by the comparator, and when input packet data is determined not to be desired data by the comparator, the input packet data is cleared from the comparator.
According to a third aspect of the present invention, a PID filter circuit includes first and second FIFO (First-in First-out) memories for storing input packet data, a first switch for switching input packet data to one of the first and the second FIFO memories, and a second switch for switching output of packet data to the FIFO that is not selected by the first switch. When data is inputted to either one of the FIFO memories, data is outputted from the other of the FIFO memories. When an inputted packet stored in one FIFO memory is determined to be desired based on comparison of the PID of the packet by the comparator, the PID filter circuit causes that data to be outputted from the FIFO memory in which it is stored by changing the switches, thereby routing next input data to the other FIFO memory.
According to a fourth aspect of the present invention, there is provided a FIFO circuit including a FIFO memory for storing input data, the FIFO memory comprising a dual port memory that is capable of executing a write operation and a read operation independently. A write pointer maintains a write address for the dual port memory, and a read pointer maintains a read address for the dual port memory. A write control section increments the value of the write pointer when data is written, and if the comparator subsequently provides a control signal indicating that the input data is not desired, the write control section decrements the value of the write pointer in accordance with the quantity of the data already stored so that future data can be written over the undesired data. A read control section increments the value of the read pointer when data is read out. The FIFO does not respond to a read demand if the difference between the read pointer and the write pointer is less than a predetermined amount.
As stated above, the PID filter circuit according to the invention stores comparison values in the comparison value table, and the comparator reads words of the comparison values from the comparison value table successively and compares those values word by word with the PID of an input data packet. For that reason, if the length of the PID is long, the comparison value table can store values for comparison to successive sections of the PID, thus still requiring only one comparator.
In the configuration in which the FIFO memory is provided, input packet data is stored in the FIFO memory and is maintained in the FIFO memory until it is determined whether the input packet is desired. If the input packet data is not desired, it is superseded in response to the output of the comparator. For that reason, even if the PID within the packet data does not have a fixed position, the circuit can provide packet filtering without changing the circuit configuration.
The above and further objects and novel features of the invention will be more fully understood from the following detailed description when the same is read in connection with the accompanying drawings. It should be expressly understood, however, that the drawings are for purpose of illustration only and are not intended as a definition of the limits of the invention.